20UPGFC0142187 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: cold

Config: 68dafbadfc2f5b6275d41b45

This Revision: 68dafbadfc2f5b6275d41b46

Latest Revision: 68dafbcbfc2f5b6275d41b75

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA8
SldoTrimD8

Parameter

ADCcalPar
  • -1.0
  • 0.188
  • 10000.0
InjCap7.511000000000001
KSenseInA21090.727
KSenseInD21837.07
Name0x22b6b
ChipId13
NfDSLDO1.2609518358404688
NfASLDO1.2616232007374892
NfACB1.2601090586293147
VcalPar
  • 13.839
  • 0.201
IrefTrim10
KSenseShuntA21693.0
KSenseShuntD22461.0
KShuntA993.981
KShuntD981.592

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA8
SldoTrimD8
Parameter
ADCcalPar
  • -1.0
  • 0.188
  • 10000.0
InjCap7.511000000000001
KSenseInA21090.727
KSenseInD21837.07
Name0x22b6b
ChipId13
NfDSLDO1.2609518358404688
NfASLDO1.2616232007374892
NfACB1.2601090586293147
VcalPar
  • 13.839
  • 0.201
IrefTrim10
KSenseShuntA21693.0
KSenseShuntD22461.0
KShuntA993.981
KShuntD981.592