20UPGFC0142426 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68dafba95dcff4364d6a2af2

This Revision: 6920d5ac948273b4430bad34

Latest Revision: 6920d5ac948273b4430bad34

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	8
SldoTrimD	8

Parameter

ADCcalPar	-1.0 0.188 10000.0
InjCap	7.457
KSenseInA	20978.425
KSenseInD	21688.301
Name	0x22c5a
ChipId	12
NfDSLDO	1.2582033436236408
NfASLDO	1.2590461264541148
NfACB	1.257589112069228
VcalPar	15.692000000000002 0.201
IrefTrim	7

KSenseShuntA	21578.0
KSenseShuntD	22308.0
KShuntA	983.924
KShuntD	984.174

PixelConfig

Diff from previous revision 690ac4422ee93469f0aced9e

No diff is present.