20UPGFC0142154 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68dafba7fc2f5b6275d41b38

This Revision: 68dafbc5fc2f5b6275d41b6c

Latest Revision: 68dafbc5fc2f5b6275d41b6c

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	9
SldoTrimD	9

Parameter

ADCcalPar	1.283 0.18 10000.0
InjCap	7.693999999999999
KSenseInA	20931.278
KSenseInD	21933.694
Name	0x22b4a
ChipId	12
NfDSLDO	1.258927653788998
NfASLDO	1.259584736517083
NfACB	1.2578848920683419
VcalPar	11.324 0.193
IrefTrim	6

KSenseShuntA	21529.0
KSenseShuntD	22560.0
KShuntA	983.006
KShuntD	1000.248

PixelConfig

Diff from previous revision 68dafba7fc2f5b6275d41b39

No diff is present.