20UPGFC0142116 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68dafba14a9a21e631a04501

This Revision: None

Latest Revision: 68dafba44a9a21e631a04517

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	8
SldoTrimD	8

Parameter

ADCcalPar	-1.0 0.181 10000.0
InjCap	8.361
KSenseInA	21160.459
KSenseInD	21504.874
Name	0x22b24
ChipId	12
NfDSLDO	1.2438926231181187
NfASLDO	1.243921192408605
NfACB	1.242364166077114
VcalPar	10.52 0.194
IrefTrim	6

KSenseShuntA	21765.0
KSenseShuntD	22119.0
KShuntA	1014.579
KShuntD	985.635

PixelConfig

Diff from previous revision None

No diff is present.