20UPGFC0142116 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: warm

Config: 68dafba04a9a21e631a044fd

This Revision: 68dafba44a9a21e631a04515

Latest Revision: 68dafba44a9a21e631a04515

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	350
DiffPreampL	550
DiffPreampM	550
DiffPreampR	550
DiffPreampT	550
DiffPreampTL	550
DiffPreampTR	550
DiffVff	60
EnCoreCol0	65535
EnCoreCol1	65535
EnCoreCol2	65535

EnCoreCol3	63
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	9
SldoTrimD	9

Parameter

ADCcalPar	10.0 0.18 10000.0
InjCap	7.46
KSenseInA	21160.459
KSenseInD	21504.874
Name	0x22b24
ChipId	12
NfDSLDO	1.2438926231181187
NfASLDO	1.243921192408605
NfACB	1.242364166077114
VcalPar	-3.0 0.19
IrefTrim	6

KSenseShuntA	21765.0
KSenseShuntD	22119.0
KShuntA	1014.579
KShuntD	985.635

PixelConfig

Diff from previous revision 68dafba04a9a21e631a044fe

No diff is present.