20UPGFC0142220 Chip Configuration

Stage: MODULE/COMPLETE

Branch: LP

Config: 68daf012fc2f5b6275d3d159

This Revision: 68daf012fc2f5b6275d3d15a

Latest Revision: 68daf012fc2f5b6275d3d15a

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA7
SldoTrimD6

Parameter

ADCcalPar
  • 3.894
  • 0.188
  • 10000.0
InjCap7.709999999999999
KSenseInA21064.906
KSenseInD21993.453
Name0x22b8c
ChipId15
NfDSLDO1.2617265219934586
NfASLDO1.2615979653293437
NfACB1.2603409668357748
VcalPar
  • 11.901
  • 0.2
IrefTrim10
KSenseShuntA21667.0
KSenseShuntD22622.0
KShuntA1013.392
KShuntD984.498

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA7
SldoTrimD6
Parameter
ADCcalPar
  • 3.894
  • 0.188
  • 10000.0
InjCap7.709999999999999
KSenseInA21064.906
KSenseInD21993.453
Name0x22b8c
ChipId15
NfDSLDO1.2617265219934586
NfASLDO1.2615979653293437
NfACB1.2603409668357748
VcalPar
  • 11.901
  • 0.2
IrefTrim10
KSenseShuntA21667.0
KSenseShuntD22622.0
KShuntA1013.392
KShuntD984.498