20UPGFC0142135 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68daf0004a9a21e631a044e4

This Revision: 68daf0004a9a21e631a044e5

Latest Revision: 6920d5bc59eb6194df7f39f0

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	9
SldoTrimD	10

Parameter

ADCcalPar	-1.0 0.186 10000.0
InjCap	7.758
KSenseInA	21136.463
KSenseInD	21655.834
Name	0x22b37
ChipId	15
NfDSLDO	1.2532727784891358
NfASLDO	1.253972707438348
NfACB	1.251744362212285
VcalPar	13.039 0.198
IrefTrim	9

KSenseShuntA	21740.0
KSenseShuntD	22275.0
KShuntA	1001.445
KShuntD	982.221

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	9
SldoTrimD	10

Parameter

ADCcalPar	-1.0 0.186 10000.0
InjCap	7.758
KSenseInA	21136.463
KSenseInD	21655.834
Name	0x22b37
ChipId	15
NfDSLDO	1.2532727784891358
NfASLDO	1.253972707438348
NfACB	1.251744362212285
VcalPar	13.039 0.198
IrefTrim	9
KSenseShuntA	21740.0
KSenseShuntD	22275.0
KShuntA	1001.445
KShuntD	982.221