20UPGFC0142135 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: cold

Config: 68daefff4a9a21e631a044e2

This Revision: 68daefff4a9a21e631a044e3

Latest Revision: 68daefff4a9a21e631a044e3

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA9
SldoTrimD10

Parameter

ADCcalPar
  • -1.0
  • 0.186
  • 10000.0
InjCap7.758
KSenseInA21136.463
KSenseInD21655.834
Name0x22b37
ChipId15
NfDSLDO1.2532727784891358
NfASLDO1.253972707438348
NfACB1.251744362212285
VcalPar
  • 13.039
  • 0.198
IrefTrim9
KSenseShuntA21740.0
KSenseShuntD22275.0
KShuntA1001.445
KShuntD982.221

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA9
SldoTrimD10
Parameter
ADCcalPar
  • -1.0
  • 0.186
  • 10000.0
InjCap7.758
KSenseInA21136.463
KSenseInD21655.834
Name0x22b37
ChipId15
NfDSLDO1.2532727784891358
NfASLDO1.253972707438348
NfACB1.251744362212285
VcalPar
  • 13.039
  • 0.198
IrefTrim9
KSenseShuntA21740.0
KSenseShuntD22275.0
KShuntA1001.445
KShuntD982.221