20UPGFC0142232 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68daefe44a9a21e631a044d5

This Revision: 6920d5b859eb6194df7f39e7

Latest Revision: 6920d5b859eb6194df7f39e7

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	10
SldoTrimD	7

Parameter

ADCcalPar	-1.0 0.188 10000.0
InjCap	7.654
KSenseInA	21221.379
KSenseInD	21313.944
Name	0x22b98
ChipId	14
NfDSLDO	1.2596864131462013
NfASLDO	1.260672027380806
NfACB	1.2591293268396855
VcalPar	14.225 0.201
IrefTrim	15

KSenseShuntA	21828.0
KSenseShuntD	21923.0
KShuntA	990.335
KShuntD	995.261

PixelConfig

Diff from previous revision 690ac4a69e9eb4cb71f94a2e

No diff is present.