20UPGFC0142169 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68daefd74a9a21e631a044c8

This Revision: 6920d5b459eb6194df7f39de

Latest Revision: 6920d5b459eb6194df7f39de

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	9
SldoTrimD	8

Parameter

ADCcalPar	3.915 0.186 10000.0
InjCap	7.562000000000001
KSenseInA	21062.45
KSenseInD	21793.915
Name	0x22b59
ChipId	13
NfDSLDO	1.2591721796324944
NfASLDO	1.2604720476810312
NfACB	1.2590436212540679
VcalPar	14.279 0.2
IrefTrim	8

KSenseShuntA	21664.0
KSenseShuntD	22417.0
KShuntA	1003.161
KShuntD	984.416

PixelConfig

Diff from previous revision 690ac4a29e9eb4cb71f94a25

No diff is present.