20UPGFC0142211 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68daefd34a9a21e631a044bb

This Revision: 690ac49f9e9eb4cb71f94a1c

Latest Revision: 6920d5af59eb6194df7f39d5

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	9
SldoTrimD	7

Parameter

ADCcalPar	-1.0 0.187 10000.0
InjCap	7.965000000000001
KSenseInA	21322.421
KSenseInD	21502.849
Name	0x22b83
ChipId	12
NfDSLDO	1.2604678455752722
NfASLDO	1.260796382558208
NfACB	1.259639361009608
VcalPar	13.234 0.2
IrefTrim	12

KSenseShuntA	21932.0
KSenseShuntD	22117.0
KShuntA	1024.821
KShuntD	983.001

PixelConfig

Diff from previous revision 6903dbcc7d93cd4c851fdfe1

No diff is present.