20UPGFC0142294 Chip Configuration

Stage: MODULE/POST_PARYLENE_COLD

Branch: LP

Config: 68c97c44118b3d6f4d48cfe1

This Revision: 68c97c44118b3d6f4d48cfe2

Latest Revision: 68c97c44118b3d6f4d48cfe2

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	9
SldoTrimD	6

Parameter

ADCcalPar	0.792 0.192 10000.0
InjCap	7.852
KSenseInA	21408.034
KSenseInD	21575.626
Name	0x22bd6
ChipId	15
NfDSLDO	1.2552178925800983
NfASLDO	1.256132097684341
NfACB	1.254746505573223
VcalPar	12.841 0.204
IrefTrim	9

KSenseShuntA	22020.0
KSenseShuntD	22192.0
KShuntA	1006.976
KShuntD	993.017

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	9
SldoTrimD	6

Parameter

ADCcalPar	0.792 0.192 10000.0
InjCap	7.852
KSenseInA	21408.034
KSenseInD	21575.626
Name	0x22bd6
ChipId	15
NfDSLDO	1.2552178925800983
NfASLDO	1.256132097684341
NfACB	1.254746505573223
VcalPar	12.841 0.204
IrefTrim	9
KSenseShuntA	22020.0
KSenseShuntD	22192.0
KShuntA	1006.976
KShuntD	993.017