20UPGFC0142184 Chip Configuration

Stage: MODULE/POST_PARYLENE_COLD

Branch: LP

Config: 68c97c36118b3d6f4d48cfcd

This Revision: 68c97c36118b3d6f4d48cfce

Latest Revision: 68c97c36118b3d6f4d48cfce

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA9
SldoTrimD9

Parameter

ADCcalPar
  • 0.43
  • 0.19
  • 10000.0
InjCap7.635000000000001
KSenseInA20865.583
KSenseInD21808.848
Name0x22b68
ChipId14
NfDSLDO1.2607333674288317
NfASLDO1.2618903966919375
NfACB1.260904779171514
VcalPar
  • 12.735
  • 0.203
IrefTrim12
KSenseShuntA21462.0
KSenseShuntD22432.0
KShuntA1001.393
KShuntD969.804

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA9
SldoTrimD9
Parameter
ADCcalPar
  • 0.43
  • 0.19
  • 10000.0
InjCap7.635000000000001
KSenseInA20865.583
KSenseInD21808.848
Name0x22b68
ChipId14
NfDSLDO1.2607333674288317
NfASLDO1.2618903966919375
NfACB1.260904779171514
VcalPar
  • 12.735
  • 0.203
IrefTrim12
KSenseShuntA21462.0
KSenseShuntD22432.0
KShuntA1001.393
KShuntD969.804