20UPGFC0142133 Chip Configuration

Stage: MODULE/POST_PARYLENE_COLD

Branch: LP

Config: 68c97c28118b3d6f4d48cfb9

This Revision: None

Latest Revision: 68c97c28118b3d6f4d48cfba

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	6
SldoTrimD	7

Parameter

ADCcalPar	2.076 0.183 10000.0
InjCap	7.842
KSenseInA	21104.051
KSenseInD	21911.812
Name	0x22b35
ChipId	13
NfDSLDO	1.2536197801075135
NfASLDO	1.2545625446922666
NfACB	1.25266273121087
VcalPar	13.435 0.196
IrefTrim	10

KSenseShuntA	21707.0
KSenseShuntD	22538.0
KShuntA	990.002
KShuntD	968.701

PixelConfig

Diff from previous revision None

No diff is present.