20UPGFC0142179 Chip Configuration

Stage: MODULE/POST_PARYLENE_COLD

Branch: LP

Config: 68c97c1f118b3d6f4d48cfa5

This Revision: 68c97c1f118b3d6f4d48cfa6

Latest Revision: 68c97c1f118b3d6f4d48cfa6

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA11
SldoTrimD8

Parameter

ADCcalPar
  • -1.0
  • 0.185
  • 10000.0
InjCap7.925
KSenseInA21167.039
KSenseInD21639.071
Name0x22b63
ChipId12
NfDSLDO1.2624264416091957
NfASLDO1.2622693167974997
NfACB1.261397988296276
VcalPar
  • 13.542
  • 0.197
IrefTrim11
KSenseShuntA21772.0
KSenseShuntD22257.0
KShuntA999.3
KShuntD980.744

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA11
SldoTrimD8
Parameter
ADCcalPar
  • -1.0
  • 0.185
  • 10000.0
InjCap7.925
KSenseInA21167.039
KSenseInD21639.071
Name0x22b63
ChipId12
NfDSLDO1.2624264416091957
NfASLDO1.2622693167974997
NfACB1.261397988296276
VcalPar
  • 13.542
  • 0.197
IrefTrim11
KSenseShuntA21772.0
KSenseShuntD22257.0
KShuntA999.3
KShuntD980.744