20UPGFC0141652 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68a3a47f6c157a77da903603

This Revision: 68c248a766da353b11fd8de9

Latest Revision: 68c248a766da353b11fd8de9

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	13
SldoTrimD	8

Parameter

ADCcalPar	-1.0 0.182 10000.0
InjCap	7.742
KSenseInA	21306.933
KSenseInD	21418.717
Name	0x22954
ChipId	15
NfDSLDO	1.2660192094960563
NfASLDO	1.266076344838852
NfACB	1.2647622319545577
VcalPar	11.217 0.194
IrefTrim	7

KSenseShuntA	21916.0
KSenseShuntD	22031.0
KShuntA	985.995
KShuntD	980.986

PixelConfig

Diff from previous revision 68c124753b237a41e9e59fb7

No diff is present.