20UPGFC0141764 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68a3a47e6c157a77da9035fe

This Revision: 68a5f38a1450bb60682dbc96

Latest Revision: 68c248a366da353b11fd8de0

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	12
SldoTrimD	11

Parameter

ADCcalPar	-1.0 0.187 10000.0
InjCap	7.852
KSenseInA	21403.879
KSenseInD	21790.737
Name	0x229c4
ChipId	14
NfDSLDO	1.2619559481010407
NfASLDO	1.2618416728439825
NfACB	1.2616416911441306
VcalPar	12.27 0.199
IrefTrim	6

KSenseShuntA	22015.0
KSenseShuntD	22413.0
KShuntA	1025.416
KShuntD	977.887

PixelConfig

Diff from previous revision 68a3a47e6c157a77da9035ff

No diff is present.