20UPGFC0141683 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68a3a0ad6c157a77da9035f0

This Revision: 68c1246f3b237a41e9e59fa5

Latest Revision: 68c248a066da353b11fd8dd7

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	9
SldoTrimD	6

Parameter

ADCcalPar	3.867 0.191 10000.0
InjCap	7.864
KSenseInA	21279.724
KSenseInD	22140.282
Name	0x22973
ChipId	13
NfDSLDO	1.264018759163577
NfASLDO	1.26494723943644
NfACB	1.263290259257177
VcalPar	10.38 0.203
IrefTrim	7

KSenseShuntA	21888.0
KSenseShuntD	22773.0
KShuntA	1000.275
KShuntD	995.332

PixelConfig

Diff from previous revision 68b91156f3be1a57922552f2

No diff is present.