20UPGFC0141682 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68a3a0a66c157a77da9035e3

This Revision: None

Latest Revision: 68c2489d66da353b11fd8dce

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	8
SldoTrimD	5

Parameter

ADCcalPar	-1.0 0.185 10000.0
InjCap	7.778
KSenseInA	21597.077
KSenseInD	21516.499
Name	0x22972
ChipId	12
NfDSLDO	1.2645245631036983
NfASLDO	1.2655530267024542
NfACB	1.2635389521548905
VcalPar	13.684 0.198
IrefTrim	6

KSenseShuntA	22214.0
KSenseShuntD	22131.0
KShuntA	1032.104
KShuntD	987.152

PixelConfig

Diff from previous revision None

No diff is present.