20UPGFC0141682 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: cold

Config: 68a3a0a56c157a77da9035e1

This Revision: 68a5f3751450bb60682dbc81

Latest Revision: 68a5f3751450bb60682dbc81

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA8
SldoTrimD5

Parameter

ADCcalPar
  • -1.0
  • 0.185
  • 10000.0
InjCap7.778
KSenseInA21597.077
KSenseInD21516.499
Name0x22972
ChipId12
NfDSLDO1.2645245631036983
NfASLDO1.2655530267024542
NfACB1.2635389521548905
VcalPar
  • 13.684
  • 0.198
IrefTrim6
KSenseShuntA22214.0
KSenseShuntD22131.0
KShuntA1032.104
KShuntD987.152

PixelConfig

Diff from previous revision 68a3a0a56c157a77da9035e2

No diff is present.