20UPGFC0141747 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68a39b2aa255cfa0a64edc5c

This Revision: 68b8f4a9c5ac9bed789f620c

Latest Revision: 68c46be7ad3217a95579c60e

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	8
SldoTrimD	6

Parameter

ADCcalPar	1.882 0.199 10000.0
InjCap	7.862
KSenseInA	21321.258
KSenseInD	21737.71
Name	0x229b3
ChipId	15
NfDSLDO	1.2629045828361418
NfASLDO	1.263918768980346
NfACB	1.2629045828361418
VcalPar	12.571 0.211
IrefTrim	13

KSenseShuntA	21930.0
KSenseShuntD	22359.0
KShuntA	1000.754
KShuntD	989.355

PixelConfig

Diff from previous revision 68a39b2aa255cfa0a64edc5d

No diff is present.