20UPGFC0141716 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68a39b26a255cfa0a64edc4f

This Revision: 68c2f444b7d71f50a6c3d272

Latest Revision: 68c46be4ad3217a95579c605

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	11
SldoTrimD	10

Parameter

ADCcalPar	-1.0 0.185 10000.0
InjCap	7.76
KSenseInA	21093.081
KSenseInD	21513.713
Name	0x22994
ChipId	14
NfDSLDO	1.2646109620146642
NfASLDO	1.2659679173587812
NfACB	1.2639681936937666
VcalPar	12.149 0.198
IrefTrim	6

KSenseShuntA	21696.0
KSenseShuntD	22128.0
KShuntA	1011.211
KShuntD	1009.877

PixelConfig

Diff from previous revision 68b8f4a6c5ac9bed789f6203

No diff is present.