20UPGFC0141619 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68a39b22a255cfa0a64edc41

This Revision: 68b8f4a3c5ac9bed789f61fa

Latest Revision: 68c46be0ad3217a95579c5fc

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	12
SldoTrimD	11

Parameter

ADCcalPar	0.827 0.179 10000.0
InjCap	8.216
KSenseInA	20911.495
KSenseInD	21610.16
Name	0x22933
ChipId	13
NfDSLDO	1.2613803666258012
NfASLDO	1.261937456646733
NfACB	1.2605661581336696
VcalPar	13.981 0.192
IrefTrim	5

KSenseShuntA	21509.0
KSenseShuntD	22228.0
KShuntA	1001.675
KShuntD	995.205

PixelConfig

Diff from previous revision 68a39b22a255cfa0a64edc42

No diff is present.