20UPGFC0141681 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68a39b1da255cfa0a64edc34

This Revision: None

Latest Revision: 68c46bddad3217a95579c5f3

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	6
SldoTrimD	9

Parameter

ADCcalPar	1.747 0.187 10000.0
InjCap	8.69
KSenseInA	21138.665
KSenseInD	21476.905
Name	0x22971
ChipId	12
NfDSLDO	-0.014284311890197505
NfASLDO	1.2657043079666206
NfACB	1.2648901021888792
VcalPar	13.361 0.201
IrefTrim	10

KSenseShuntA	21743.0
KSenseShuntD	22091.0
KShuntA	998.75
KShuntD	989.602

PixelConfig

Diff from previous revision None

No diff is present.