20UPGFC0142260 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68a39702d220797d7931a5cf

This Revision: 68e99acbae317c571e504257

Latest Revision: 68e99acbae317c571e504257

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	8
SldoTrimD	9

Parameter

ADCcalPar	5.294 0.182 10000.0
InjCap	7.989
KSenseInA	21177.071
KSenseInD	21642.834
Name	0x22bb4
ChipId	15
NfDSLDO	1.2571622894562826
NfASLDO	1.2575622501892076
NfACB	1.2562338091834195
VcalPar	13.288 0.195
IrefTrim	9

KSenseShuntA	21782.0
KSenseShuntD	22261.0
KShuntA	1012.046
KShuntD	994.566

PixelConfig

Diff from previous revision 68e95fcbd8143174b41a2ab3

No diff is present.