20UPGFC0142221 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68a396fdd220797d7931a5c2

This Revision: 68a396fdd220797d7931a5c3

Latest Revision: 68d34f6e8b1152bfdedf1f08

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA9
SldoTrimD9

Parameter

ADCcalPar
  • -1.0
  • 0.193
  • 10000.0
InjCap7.894999999999999
KSenseInA20959.868
KSenseInD21357.844
Name0x22b8d
ChipId14
NfDSLDO1.2592310070065598
NfASLDO1.2601880431410195
NfACB1.2584310962076082
VcalPar
  • 14.341
  • 0.207
IrefTrim10
KSenseShuntA21559.0
KSenseShuntD21968.0
KShuntA976.265
KShuntD980.925

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA9
SldoTrimD9
Parameter
ADCcalPar
  • -1.0
  • 0.193
  • 10000.0
InjCap7.894999999999999
KSenseInA20959.868
KSenseInD21357.844
Name0x22b8d
ChipId14
NfDSLDO1.2592310070065598
NfASLDO1.2601880431410195
NfACB1.2584310962076082
VcalPar
  • 14.341
  • 0.207
IrefTrim10
KSenseShuntA21559.0
KSenseShuntD21968.0
KShuntA976.265
KShuntD980.925