20UPGFC0142140 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68a396f8d220797d7931a5b5

This Revision: 68ce0da501cd1f7328b49ef5

Latest Revision: 68d34f6b8b1152bfdedf1eff

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA12
SldoTrimD9

Parameter

ADCcalPar
  • 1.749
  • 0.179
  • 10000.0
InjCap7.822
KSenseInA20952.71
KSenseInD21321.204
Name0x22b3c
ChipId13
NfDSLDO1.2478429538543507
NfASLDO1.2487000182822874
NfACB1.2479857979256737
VcalPar
  • 11.555
  • 0.191
IrefTrim5
KSenseShuntA21551.0
KSenseShuntD21930.0
KShuntA998.106
KShuntD977.34

PixelConfig

Diff from previous revision 68c0cbb3a011b210c5f1811a

No diff is present.