20UPGFC0142282 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68a396f2d220797d7931a5a8

This Revision: 68e95fc2d8143174b41a2a98

Latest Revision: 68e99ac2ae317c571e50423c

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	12
SldoTrimD	11

Parameter

ADCcalPar	2.846 0.185 10000.0
InjCap	7.911999999999999
KSenseInA	21396.829
KSenseInD	21410.943
Name	0x22bca
ChipId	12
NfDSLDO	1.255766613337947
NfASLDO	1.2568807933798112
NfACB	1.2551952389575038
VcalPar	14.44 0.197
IrefTrim	8

KSenseShuntA	22008.0
KSenseShuntD	22023.0
KShuntA	997.561
KShuntD	988.152

PixelConfig

Diff from previous revision 68e826c45b3e41f59cf5e132

No diff is present.