20UPGFC0142282 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68a396f2d220797d7931a5a8

This Revision: 68b911fbc5ac9bed789f6223

Latest Revision: 68d34f678b1152bfdedf1ef5

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA12
SldoTrimD11

Parameter

ADCcalPar
  • 2.846
  • 0.185
  • 10000.0
InjCap7.911999999999999
KSenseInA21396.829
KSenseInD21410.943
Name0x22bca
ChipId12
NfDSLDO1.255766613337947
NfASLDO1.2568807933798112
NfACB1.2551952389575038
VcalPar
  • 14.44
  • 0.197
IrefTrim8
KSenseShuntA22008.0
KSenseShuntD22023.0
KShuntA997.561
KShuntD988.152

PixelConfig

Diff from previous revision 68a4f803a36b4f6ab612f89e

No diff is present.