20UPGFC0142282 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: cold

Config: 68a396f1d220797d7931a5a6

This Revision: 68a396f1d220797d7931a5a7

Latest Revision: 68a396f1d220797d7931a5a7

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	350
DiffPreampL	550
DiffPreampM	550
DiffPreampR	550
DiffPreampT	550
DiffPreampTL	550
DiffPreampTR	550
DiffVff	60
EnCoreCol0	65535
EnCoreCol1	65535
EnCoreCol2	65535

EnCoreCol3	63
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	12
SldoTrimD	11

Parameter

ADCcalPar	2.846 0.185 10000.0
InjCap	7.911999999999999
KSenseInA	21396.829
KSenseInD	21410.943
Name	0x22bca
ChipId	12
NfDSLDO	1.255766613337947
NfASLDO	1.2568807933798112
NfACB	1.2551952389575038
VcalPar	14.44 0.197
IrefTrim	8

KSenseShuntA	22008.0
KSenseShuntD	22023.0
KShuntA	997.561
KShuntD	988.152

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	350
DiffPreampL	550
DiffPreampM	550
DiffPreampR	550
DiffPreampT	550
DiffPreampTL	550
DiffPreampTR	550
DiffVff	60
EnCoreCol0	65535
EnCoreCol1	65535
EnCoreCol2	65535
EnCoreCol3	63
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	12
SldoTrimD	11

Parameter

ADCcalPar	2.846 0.185 10000.0
InjCap	7.911999999999999
KSenseInA	21396.829
KSenseInD	21410.943
Name	0x22bca
ChipId	12
NfDSLDO	1.255766613337947
NfASLDO	1.2568807933798112
NfACB	1.2551952389575038
VcalPar	14.44 0.197
IrefTrim	8
KSenseShuntA	22008.0
KSenseShuntD	22023.0
KShuntA	997.561
KShuntD	988.152