20UPGFC0156331 Chip Configuration

Stage: MODULE/QC_CROSSCHECK

Branch: LP

Config: 687fcf3f59f92f438e29f4b8

This Revision: 68f698dc61e7430a45c1a59d

Latest Revision: 68f698dc61e7430a45c1a59d

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0

DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	9
SldoTrimD	6

Parameter

ADCcalPar	2.119 0.19 10000.0
Name	0x262ab
ChipId	15
NfDSLDO	1.2568724130850837
NfASLDO	1.2575009207129475
NfACB	1.2562153369286804
VcalPar	13.74 0.203
IrefTrim	13
KSenseInA	20787.971
KSenseInD	21194.297
KSenseShuntA	21381.913028571427

KSenseShuntD	21799.848342857138
KShuntA	1008.135
KShuntD	963.492

PixelConfig

Diff from previous revision 68f6982d1df90bb75cd9978e

No diff is present.