20UPGFC0156332 Chip Configuration

Stage: MODULE/QC_CROSSCHECK

Branch: LP

Config: 687fcf3b59f92f438e29f4aa

This Revision: 68dae0a8acd15865eada395c

Latest Revision: 68f698d661e7430a45c1a594

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1

DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	8
SldoTrimD	10

Parameter

ADCcalPar	3.122 0.184 10000.0
Name	0x262ac
ChipId	14
NfDSLDO	1.2560934318984052
NfASLDO	1.2563934064482933
NfACB	1.2548649646941012
VcalPar	13.309 0.197
IrefTrim	8
KSenseInA	20949.491
KSenseInD	21195.72
KSenseShuntA	21548.047885714284

KSenseShuntD	21801.311999999998
KShuntA	1011.059
KShuntD	971.395

PixelConfig

Diff from previous revision 68dabfdf8c6cf1b6f575001c

No diff is present.