20UPGFC0156330 Chip Configuration

Stage: MODULE/QC_CROSSCHECK

Branch: LP

Config: 687fcf3859f92f438e29f49d

This Revision: 68f698271df90bb75cd9977c

Latest Revision: 68f698d261e7430a45c1a58b

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0

DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	8
SldoTrimD	10

Parameter

ADCcalPar	-1.0 0.181 10000.0
Name	0x262aa
ChipId	13
NfDSLDO	1.255609485383325
NfASLDO	1.2572664710866102
NfACB	1.255738044618925
VcalPar	12.057 0.195
IrefTrim	5
KSenseInA	20973.989
KSenseInD	21598.963
KSenseShuntA	21573.245828571427

KSenseShuntD	22216.076228571426
KShuntA	1011.45
KShuntD	990.797

PixelConfig

Diff from previous revision 68f697161df90bb75cd99754

No diff is present.