20UPGFC0156329 Chip Configuration

Stage: MODULE/QC_CROSSCHECK

Branch: LP

Config: 687fcf2459f92f438e29f490

This Revision: 68f698231df90bb75cd99773

Latest Revision: 68f698ce61e7430a45c1a582

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2

DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	7
SldoTrimD	10

Parameter

ADCcalPar	-1.0 0.19 10000.0
Name	0x262a9
ChipId	12
NfDSLDO	1.2566909071639059
NfASLDO	1.257333701198965
NfACB	1.2553196132224467
VcalPar	15.308 0.203
IrefTrim	8
KSenseInA	21259.494
KSenseInD	21761.484
KSenseShuntA	21866.90811428571

KSenseShuntD	22383.240685714285
KShuntA	1012.602
KShuntD	990.825

PixelConfig

Diff from previous revision 68f697121df90bb75cd9974b

No diff is present.