20UPGFC0156341 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 687ed3afae449964eb60161a

This Revision: 688d1245ba39689da6bc62fa

Latest Revision: 688d1245ba39689da6bc62fa

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0

DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	8
SldoTrimD	8

Parameter

ADCcalPar	4.943 0.183 10000.0
Name	0x262b5
ChipId	15
NfDSLDO	1.2552792152629944
NfASLDO	1.2560934318984052
NfACB	1.254950671708355
VcalPar	12.601 0.196
IrefTrim	7
KSenseInA	21485.86
KSenseInD	21819.609
KSenseShuntA	22099.741714285712

KSenseShuntD	22443.0264
KShuntA	986.364
KShuntD	978.788

PixelConfig

Diff from previous revision 688bffa68c3f2e8eccd4208c

No diff is present.