20UPGFC0156342 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 687ed3aaae449964eb60160d

This Revision: 688bffa28c3f2e8eccd42083

Latest Revision: 688d1241ba39689da6bc62f1

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1

DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	9
SldoTrimD	9

Parameter

ADCcalPar	-1.0 0.182 10000.0
Name	0x262b6
ChipId	14
NfDSLDO	1.2565236843920342
NfASLDO	1.2568665090203
NfACB	1.2556951915403916
VcalPar	11.427 0.194
IrefTrim	7
KSenseInA	21412.055
KSenseInD	21576.777
KSenseShuntA	22023.827999999998

KSenseShuntD	22193.256342857137
KShuntA	995.257
KShuntD	988.961

PixelConfig

Diff from previous revision 687ed3aaae449964eb60160e

No diff is present.