20UPGFC0156340 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 687ed3a3ae449964eb601600

This Revision: 688bff9f8c3f2e8eccd4207a

Latest Revision: 688d123eba39689da6bc62e8

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0

DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	6
SldoTrimD	7

Parameter

ADCcalPar	4.637 0.182 10000.0
Name	0x262b4
ChipId	13
NfDSLDO	1.255422060286751
NfASLDO	1.2568647950266891
NfACB	1.2553506377748729
VcalPar	11.866 0.194
IrefTrim	6
KSenseInA	21410.099
KSenseInD	21377.426
KSenseShuntA	22021.81611428571

KSenseShuntD	21988.2096
KShuntA	1011.899
KShuntD	994.781

PixelConfig

Diff from previous revision 687ed3a3ae449964eb601601

No diff is present.