20UPGFC0156339 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 687ed39dae449964eb6015f3

This Revision: 688d123aba39689da6bc62df

Latest Revision: 688d123aba39689da6bc62df

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2

DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	11
SldoTrimD	10

Parameter

ADCcalPar	-1.0 0.181 10000.0
Name	0x262b3
ChipId	12
NfDSLDO	1.256768993354548
NfASLDO	1.2572689526044707
NfACB	1.255640513904724
VcalPar	14.008 0.194
IrefTrim	8
KSenseInA	21227.722
KSenseInD	21662.341
KSenseShuntA	21834.228342857143

KSenseShuntD	22281.265028571426
KShuntA	1004.251
KShuntD	983.748

PixelConfig

Diff from previous revision 688bff9c8c3f2e8eccd42071

No diff is present.