20UPGFC0084915 Chip Configuration

Stage: MODULE/THERMAL_CYCLES

Branch: LP

Config: 6826389315602c057ad78493

This Revision: 6826389315602c057ad78494

Latest Revision: 6826389315602c057ad78494

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0

DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	7
SldoTrimD	9

Parameter

ADCcalPar	13.727 0.184 10000.0
Name	0x14bb3
ChipId	12
InjCap	7.980999999999999
NfDSLDO	1.2911132091281807
NfASLDO	1.2938183550888174
NfACB	1.2882649337516368
VcalPar	2.0 0.197
IrefTrim	8
KSenseInA	21251.923
KSenseInD	21747.299

KSenseShuntA	26311.904666666665
KSenseShuntD	26925.227333333332
KShuntA	1061.684
KShuntD	1050.163

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	7
SldoTrimD	9

Parameter

ADCcalPar	13.727 0.184 10000.0
Name	0x14bb3
ChipId	12
InjCap	7.980999999999999
NfDSLDO	1.2911132091281807
NfASLDO	1.2938183550888174
NfACB	1.2882649337516368
VcalPar	2.0 0.197
IrefTrim	8
KSenseInA	21251.923
KSenseInD	21747.299
KSenseShuntA	26311.904666666665
KSenseShuntD	26925.227333333332
KShuntA	1061.684
KShuntD	1050.163