20UPGFC0084917 Chip Configuration

Stage: MODULE/POST_PARYLENE_COLD

Branch: LP

Config: 682503008e9c40a968608519

This Revision: 682528108e9c40a9686086f3

Latest Revision: 682528108e9c40a9686086f3

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2

DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	10
SldoTrimD	4

Parameter

ADCcalPar	13.149 0.191 10000.0
Name	0x14bb5
ChipId	13
InjCap	7.884000000000001
NfDSLDO	1.2889931350253332
NfASLDO	1.2879041437375998
NfACB	1.2862133414750663
VcalPar	4.454 0.205
IrefTrim	14
KSenseInA	21271.791
KSenseInD	21348.013

KSenseShuntA	26336.503142857142
KSenseShuntD	26430.87323809524
KShuntA	1057.121
KShuntD	1089.833

PixelConfig

Diff from previous revision 682503ae8e9c40a96860853d

No diff is present.