20UPGFC0084916 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 6823c4dd33dc62901226c09d

This Revision: 6823c4dd33dc62901226c09e

Latest Revision: 6823c4dd33dc62901226c09e

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3

DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	11
SldoTrimD	10

Parameter

ADCcalPar	10.597 0.196 10000.0
Name	0x14bb4
ChipId	14
InjCap	7.960999999999999
NfDSLDO	1.2886475060897236
NfASLDO	1.2876745315786744
NfACB	1.2860862937738735
VcalPar	4.075 0.21
IrefTrim	11
KSenseInA	21116.564
KSenseInD	21485.122

KSenseShuntA	26144.317333333332
KSenseShuntD	26600.62723809524
KShuntA	1084.791
KShuntD	1077.982

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	11
SldoTrimD	10

Parameter

ADCcalPar	10.597 0.196 10000.0
Name	0x14bb4
ChipId	14
InjCap	7.960999999999999
NfDSLDO	1.2886475060897236
NfASLDO	1.2876745315786744
NfACB	1.2860862937738735
VcalPar	4.075 0.21
IrefTrim	11
KSenseInA	21116.564
KSenseInD	21485.122
KSenseShuntA	26144.317333333332
KSenseShuntD	26600.62723809524
KShuntA	1084.791
KShuntD	1077.982