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20UPGFC0142726 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 67f43381d04bade272d27ef9

This Revision: 67f43381d04bade272d27efa

Latest Revision: 67f43381d04bade272d27efa

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	7
SldoTrimD	8

Parameter

ADCcalPar	3.779 0.181 10000.0
Name	0x22d86
ChipId	15
InjCap	7.746
NfDSLDO	1.2607266368281198
NfASLDO	1.2613837042224851
NfACB	1.259755319810362
VcalPar	11.387 0.193
IrefTrim	3
KSenseInA	21090.01
KSenseInD	21630.113

KSenseShuntA	26111.44095238095
KSenseShuntD	26780.139904761905
KShuntA	1003.932
KShuntD	1014.654

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	7
SldoTrimD	8

Parameter

ADCcalPar	3.779 0.181 10000.0
Name	0x22d86
ChipId	15
InjCap	7.746
NfDSLDO	1.2607266368281198
NfASLDO	1.2613837042224851
NfACB	1.259755319810362
VcalPar	11.387 0.193
IrefTrim	3
KSenseInA	21090.01
KSenseInD	21630.113
KSenseShuntA	26111.44095238095
KSenseShuntD	26780.139904761905
KShuntA	1003.932
KShuntD	1014.654