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20UPGFC0142724 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 67f43381d04bade272d27ef5

This Revision: 67f43381d04bade272d27ef6

Latest Revision: 67f43381d04bade272d27ef6

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	9
SldoTrimD	9

Parameter

ADCcalPar	1.619 0.178 10000.0
Name	0x22d84
ChipId	13
InjCap	7.693999999999999
NfDSLDO	1.2597721187318192
NfASLDO	1.2602720679812565
NfACB	1.2595007177106963
VcalPar	12.015 0.191
IrefTrim	6
KSenseInA	21179.352
KSenseInD	21608.388

KSenseShuntA	26222.054857142855
KSenseShuntD	26753.242285714285
KShuntA	1000.63
KShuntD	994.228

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	9
SldoTrimD	9

Parameter

ADCcalPar	1.619 0.178 10000.0
Name	0x22d84
ChipId	13
InjCap	7.693999999999999
NfDSLDO	1.2597721187318192
NfASLDO	1.2602720679812565
NfACB	1.2595007177106963
VcalPar	12.015 0.191
IrefTrim	6
KSenseInA	21179.352
KSenseInD	21608.388
KSenseShuntA	26222.054857142855
KSenseShuntD	26753.242285714285
KShuntA	1000.63
KShuntD	994.228