20UPGFC0142690 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 67f43381d04bade272d27ef3

This Revision: 67f43381d04bade272d27ef4

Latest Revision: 67f43381d04bade272d27ef4

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA9
SldoTrimD6

Parameter

ADCcalPar
  • 8.224
  • 0.183
  • 10000.0
Name0x22d62
ChipId12
InjCap7.878999999999999
NfDSLDO1.2606678246083638
NfASLDO1.2607392456916107
NfACB1.2596536452262572
VcalPar
  • 13.266
  • 0.196
IrefTrim6
KSenseInA21179.821
KSenseInD21663.984
KSenseShuntA26222.635523809524
KSenseShuntD26822.07542857143
KShuntA1010.95
KShuntD997.087

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA9
SldoTrimD6
Parameter
ADCcalPar
  • 8.224
  • 0.183
  • 10000.0
Name0x22d62
ChipId12
InjCap7.878999999999999
NfDSLDO1.2606678246083638
NfASLDO1.2607392456916107
NfACB1.2596536452262572
VcalPar
  • 13.266
  • 0.196
IrefTrim6
KSenseInA21179.821
KSenseInD21663.984
KSenseShuntA26222.635523809524
KSenseShuntD26822.07542857143
KShuntA1010.95
KShuntD997.087