20UPGFC0132969 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 6798e4a188a06d598f0256af

This Revision: 6798e4a188a06d598f0256b0

Latest Revision: 6798e4a188a06d598f0256b0

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA9
SldoTrimD7

Parameter

ADCcalPar
  • 0.599
  • 0.185
  • 10000.0
Name0x20769
ChipId14
InjCap7.739000000000001
NfDSLDO1.2513866213165532
NfASLDO1.2552432826688893
NfACB1.2501153514633756
VcalPar
  • 12.382
  • 0.197
IrefTrim12
KSenseInA21410.513
KSenseInD21545.569
KSenseShuntA26508.25419047619
KSenseShuntD26675.46638095238
KShuntA1018.433
KShuntD991.466

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA9
SldoTrimD7
Parameter
ADCcalPar
  • 0.599
  • 0.185
  • 10000.0
Name0x20769
ChipId14
InjCap7.739000000000001
NfDSLDO1.2513866213165532
NfASLDO1.2552432826688893
NfACB1.2501153514633756
VcalPar
  • 12.382
  • 0.197
IrefTrim12
KSenseInA21410.513
KSenseInD21545.569
KSenseShuntA26508.25419047619
KSenseShuntD26675.46638095238
KShuntA1018.433
KShuntD991.466