20UPGFC0133060 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 6798e4a188a06d598f0256ad

This Revision: 6798e4a188a06d598f0256ae

Latest Revision: 6798e4a188a06d598f0256ae

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA9
SldoTrimD7

Parameter

ADCcalPar
  • 6.472
  • 0.18
  • 10000.0
Name0x207c4
ChipId13
InjCap7.901999999999999
NfDSLDO1.2548339466181802
NfASLDO1.2563195150547606
NfACB1.2541340153355605
VcalPar
  • 13.588
  • 0.194
IrefTrim6
KSenseInA21241.683
KSenseInD21965.478
KSenseShuntA26299.22657142857
KSenseShuntD27195.353714285713
KShuntA1021.371
KShuntD987.926

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA9
SldoTrimD7
Parameter
ADCcalPar
  • 6.472
  • 0.18
  • 10000.0
Name0x207c4
ChipId13
InjCap7.901999999999999
NfDSLDO1.2548339466181802
NfASLDO1.2563195150547606
NfACB1.2541340153355605
VcalPar
  • 13.588
  • 0.194
IrefTrim6
KSenseInA21241.683
KSenseInD21965.478
KSenseShuntA26299.22657142857
KSenseShuntD27195.353714285713
KShuntA1021.371
KShuntD987.926