20UPGFC0094503 Chip Configuration

Stage: MODULE/FINAL_METROLOGY

Branch: LP

Config: 67644b0c588d51321df8594c

This Revision: 67644b0c588d51321df8594d

Latest Revision: 67644b0c588d51321df8594d

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA7
SldoTrimD5

Parameter

ADCcalPar
  • 7.768
  • 0.195
  • 10000.0
Name0x17127
ChipId15
InjCap7.815999999999999
NfDSLDO1.2885507499388749
NfASLDO1.287316629634455
NfACB1.2856807027192945
VcalPar
  • 3.364
  • 0.208
IrefTrim15
KSenseInA21363.655
KSenseInD21621.06
KSenseShuntA26450.239523809523
KSenseShuntD26768.931428571428
KShuntA1072.665
KShuntD1072.582

PixelConfig

Diff from previous revision None

RD53B
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA7
SldoTrimD5
Parameter
ADCcalPar
  • 7.768
  • 0.195
  • 10000.0
Name0x17127
ChipId15
InjCap7.815999999999999
NfDSLDO1.2885507499388749
NfASLDO1.287316629634455
NfACB1.2856807027192945
VcalPar
  • 3.364
  • 0.208
IrefTrim15
KSenseInA21363.655
KSenseInD21621.06
KSenseShuntA26450.239523809523
KSenseShuntD26768.931428571428
KShuntA1072.665
KShuntD1072.582