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20UPGFC0094519 Chip Configuration

Stage: MODULE/FINAL_METROLOGY

Branch: LP

Config: 67644b03588d51321df85938

This Revision: 67644b03588d51321df85939

Latest Revision: 67644b03588d51321df85939

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	13
SldoTrimD	8

Parameter

ADCcalPar	3.9569999999999994 0.179 10000.0
Name	0x17137
ChipId	14
InjCap	7.868000000000001
NfDSLDO	1.2853635815221789
NfASLDO	1.284488530703871
NfACB	1.2823511114919384
VcalPar	4.637 0.191
IrefTrim	9
KSenseInA	21268.601
KSenseInD	21499.597

KSenseShuntA	26332.55361904762
KSenseShuntD	26618.548666666666
KShuntA	1067.405
KShuntD	1038.579

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	13
SldoTrimD	8

Parameter

ADCcalPar	3.9569999999999994 0.179 10000.0
Name	0x17137
ChipId	14
InjCap	7.868000000000001
NfDSLDO	1.2853635815221789
NfASLDO	1.284488530703871
NfACB	1.2823511114919384
VcalPar	4.637 0.191
IrefTrim	9
KSenseInA	21268.601
KSenseInD	21499.597
KSenseShuntA	26332.55361904762
KSenseShuntD	26618.548666666666
KShuntA	1067.405
KShuntD	1038.579