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20UPGFC0094534 Chip Configuration

Stage: MODULE/FINAL_METROLOGY

Branch: LP

Config: 67644afa588d51321df85924

This Revision: 67644afb588d51321df85925

Latest Revision: 67644afb588d51321df85925

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	7
SldoTrimD	6

Parameter

ADCcalPar	10.913 0.192 10000.0
Name	0x17146
ChipId	13
InjCap	7.797
NfDSLDO	1.2854180943557603
NfASLDO	1.2849011413155236
NfACB	1.2819143015274879
VcalPar	3.419 0.206
IrefTrim	14
KSenseInA	21391.919
KSenseInD	21589.651

KSenseShuntA	26485.233047619047
KSenseShuntD	26730.044095238096
KShuntA	1070.207
KShuntD	1013.001

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	7
SldoTrimD	6

Parameter

ADCcalPar	10.913 0.192 10000.0
Name	0x17146
ChipId	13
InjCap	7.797
NfDSLDO	1.2854180943557603
NfASLDO	1.2849011413155236
NfACB	1.2819143015274879
VcalPar	3.419 0.206
IrefTrim	14
KSenseInA	21391.919
KSenseInD	21589.651
KSenseShuntA	26485.233047619047
KSenseShuntD	26730.044095238096
KShuntA	1070.207
KShuntD	1013.001