20UPGFC0094502 Chip Configuration

Stage: MODULE/FINAL_METROLOGY

Branch: LP

Config: 67644af1588d51321df85910

This Revision: None

Latest Revision: 67644af1588d51321df85911

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane4
SldoTrimA8
SldoTrimD6

Parameter

ADCcalPar
  • 6.59
  • 0.189
  • 10000.0
Name0x17126
ChipId12
InjCap7.827
NfDSLDO1.2879720044845622
NfASLDO1.2864494261394035
NfACB1.2846539328078481
VcalPar
  • 3.085
  • 0.201
IrefTrim12
KSenseInA21280.825
KSenseInD21543.411
KSenseShuntA26347.688095238096
KSenseShuntD26672.79457142857
KShuntA1076.091
KShuntD1021.165

PixelConfig

Diff from previous revision None

No diff is present.